2020 International Workshop on Performance, Portability & Productivity in HPC

Submitting a Paper

Authors are invited to submit original papers for potential presentation as part of the P3HPC workshop. Submitted papers will be peer-reviewed and accepted papers will be published by the IEEE Technical Consortium on High Performance Computing (TCHPC) in the IEEE Xplore Digital Library.

Papers must be submitted electronically using the SC20 submissions web site.

Important Dates

  • 6/30/2020: Submissions open
  • 9/11/2020: Paper submissions due (9/8/2020)
  • 9/22/2020: Author Notification
  • 10/7/2020: Camera ready submissions due
  • 10/7/2020: Recorded talks uploaded
  • 11/13/2020: P3HPC Workshop


  • Papers may be at most 10 pages long, including tables, figures and appendices. References and the required Reproducibilty Appendix (see below) are not included in this maximum page count. Papers must be at least 6 pages long, not including references and the Reproducibility Appendix.

  • Submissions must be formatted according to the IEEE Conference Proceedings format as implemented by the IEEE Conference Proceedings Word and LaTex/BibTex templates (use “conference” mode with LaTeX). Authors must not change the template (e.g. to change fonts, spacing, margins).

Reproducibility Appendix

The P3HPC workshop will follow a reproducibility initiative similar to the SC20 Technical Papers Reproducibilty Initiative: authors are encouraged to submit an appendix of no more than two pages detailing available artifacts (software, data, and documentation) and any steps taken to increase the trustworthiness of their results.

The nature of performance portability involves demonstrated performance across multiple architectures, hence authors should describe artifact components across all architectures employed, such as compiler, runtime and application configurations. Authors should clearly document and explain the reasoning behind such configuration differences, to assist future researchers seeking to reproduce their experiments on future architectures.

A reproducibility appendix template can be found here.